/*
 * clk.h - head file for lombo clk dirver
 *
 * Copyright (C) 2016-2018, LomboTech Co.Ltd.
 * Author: lomboswer <lomboswer@lombotech.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */

#ifndef __LOMBO_CLK_H
#define __LOMBO_CLK_H

#include <mach/debug.h>

/* redefine mode name, for PTR_XXX */
#undef MOD_NAME
#define MOD_NAME	"CLK"

/* max freq-div count for modules */
#define MAX_FD_CNT_MOD		48

/* max freq-div count for pll */
#define MAX_FD_CNT_PLL		32

/* audio pll name (POST_DIV reg field bypassed) */
#define AUDIO_PLL_NAME		"audio_pll"

#define LOMBO_CLK_SAVE		BIT(31)
#define LOMBO_CLK_SAVE_CLEAR	BIT(30)

#define to_clk_divider2(_hw) container_of(_hw, struct clk_divider2, hw)
#define to_clock_pll(_hw) container_of(_hw, struct clock_pll, hw)
#define to_clock_adpll(_hw) container_of(_hw, struct clock_adpll, hw)

/* reg index in clock_pll->reg[] */
enum {
	ENABLE = 0, FACTOR, TUNE0, TEST,
	STATUS, MODE, NFAC, TUNE1, TUNE2,
	MAX_PLL_REGS = TUNE2 + 1,
};

/* reg index in adpll->reg[] */
enum {
	AD_FACTOR = 0, AD_TUNE0, AD_TUNE1,
	AD_STATUS, AD_TUNE2, AD_NFAC_TUNE,
	AD_MAX_PLL_REGS = AD_NFAC_TUNE + 1,
};

/* element index in clock_pll->en_shift[] */
enum { ENP = 0, ENM, OEN, LOCK };

/* element index in clock_pll->fac_shift[] or fac_width[] */
enum { PREV = 0, POST, FAC };

/* element index in adpll->fac_shift[] or fac_width[] */
enum { AD_POST = 0, AD_FAC };

struct rate_dval_table {
	u32	rate;
	u32	parent_rate;
	/*
	 * val0 and val1 are the orignal val read from reg bits
	 * NOT the corresponding division value. eg: val0 is 3
	 * while the corresponding division is 8(2^3)
	 */
	int		val0;
	int		val1;
};

/* module clock with two dividers */
struct clk_divider2 {
	struct clk_hw	hw;
	void __iomem	*reg;
	/*
	 * use u32(not u8) for of_property_read_u32_array
	 */
	u32		shift[2];
	u32		width[2];
	u8		flags[2]; /* divider flags for div0 and div1 */
	const struct clk_div_table *table[2];
	spinlock_t	lock;
	/*
	 * the freq-div table
	 */
	int		fd_cnt;	/* element cnt of table */
	struct rate_dval_table fd_table[MAX_FD_CNT_MOD];
	spinlock_t	fd_lock;
};

/* pll clock's freq-factor-div table */
struct pll_fac_dval_table {
	u32	rate;		/* pll clock rate in HZ */
	u32	parent_rate;	/* parent clock rate in HZ */
	u32	factor;		/* pll factor N */
	u32	prev_val;	/* PREV_DIV = prev_val + 1 */
	u32	post_val;	/* PREV_DIV = prev_val + 1 */
	u32	nfrac;
};

/* adpll clock's freq-factor-div table */
struct adpll_fac_dval_table {
	u32	rate;		/* pll clock rate in HZ */
	u32	parent_rate;	/* parent clock rate in HZ */
	int	factor;		/* pll factor N */
	int	post_val;	/* PREV_DIV = prev_val + 1 */
};

/* pll clock struct */
struct clock_pll {
	struct clk_hw	hw;
	void __iomem	*reg[MAX_PLL_REGS]; /* regs' address list for pll */
	u32		reg_cnt;	/* actual reg cnt, <= MAX_PLL_REGS */
	u32		en_shift[4];	/* bit index for enm enp oen lock */
	u32		fac_shift[3];	/* bit index for prevdiv postdiv n */
	u32		fac_width[3];	/* bit width for prevdiv postdiv n */
	u8		flags[2];	/* divider flags for prevdiv postdiv */
	const struct clk_div_table *table[2]; /* prevdiv and postdiv table */
	spinlock_t	lock;
	struct mutex	prepare_lock;	/* lock for prepare, can sleep */

	/*
	 * the pll freq and factor/div table
	 */
	int		fd_cnt;		/* element cnt of table */
	struct pll_fac_dval_table fd_table[MAX_FD_CNT_PLL];
	spinlock_t	fd_lock;
};

/* adpll clock struct */
struct clock_adpll {
	struct clk_hw   hw;
	void __iomem    *reg[AD_MAX_PLL_REGS];
	u32             reg_cnt;
	u32		*en_shift;
	u32		fac_shift[2];
	u32		fac_width[2];
	u8              flags[2];       /* divider flags for prevdiv postdiv */
	const struct clk_div_table *table; /* prevdiv and postdiv table */
	spinlock_t      lock;
	struct mutex    prepare_lock;   /* lock for prepare, can sleep */

	/*
	 * the pll freq and factor/div table
	 */
	int             fd_cnt;         /* element cnt of table */
	struct adpll_fac_dval_table fd_table[MAX_FD_CNT_PLL];
	spinlock_t      fd_lock;
};

#ifdef CONFIG_PM_SLEEP
/**
 * struct lombo_clk_reg_dump: register dump of clock controller registers.
 * @addr: clock register address
 * @value: the value to be register
 * @disable: clock register clean or not
 */
struct lombo_clk_reg_dump {
	struct list_head node;
	struct clk *clk;
	void __iomem *addr;
	u32 value;
	bool clear;
};

int lombo_clk_save(struct clk *clk, void __iomem *base, bool clear);
int lombo_clk_get_pm_flag(struct device_node *node, u32 *flag);
#endif

int is_audio_pll_clk(const char *name);
unsigned long audio_pll_recalc_rate(struct clk_hw *hw,
				unsigned long parent_rate);
void set_audio_pll_frac_mode(struct clk_hw *hw);

unsigned int __get_div(u8 flags, unsigned int val,
				const struct clk_div_table *table);
int __calc_val(u8 flags, int div, u32 div_width,
				const struct clk_div_table *table,
				bool exact_match);
int __init_divider_table(struct device_node *node, unsigned long *table_out);
unsigned int _get_table_div(const struct clk_div_table *table,
				unsigned int val);
#endif /* __LOMBO_CLK_H */
